FIG. 1 illustrates a prior art programming and verification scheme used in field programmable logic devices. In a typical embodiment of FIG. 1 Array Data Shift Register (ADSR) Select Circuit 122 is programmed to select individual flip-flops 102A-102N in ADSR 104. Once selected, individual flip-flops 102A-102N are enabled and can accept programming in the form of data or sequential instructions. Each flip-flop 102A-102N contains at least one programmable bit. The programmable bit is programmed when data is input to the D-input of selected flip-flop(s) 102A-102N. The programmable bits, taken together, can define at least one programmable address in ADSR 104. After data is input to flip-flops 102A-102N, control for the program is transferred from ADSR 104 to Product-Term Logic Gates 112A-112N. Program Mode Controller 127 sets the Product-Term Logic Gates' second input to a logical "1" while the circuit is being programmed. (This second input is used as a data line after the circuit is programmed and while it is being used by a user.) These programming operations must be carried out in a serial fashion, completely loading the data into one of the selected flip-flops before loading the next. Also, the structural limitations associated with prior art macrocell devices, such as that shown and described in FIG. 1, are such that in order to expand the circuit's capability a typical prior art circuit may have a mirrored (or second identical) macrocell also using MSR 126. In such a case, programming and verification steps take twice as long because the same operation must be serially processed through MSR. This serial limitation occurs because all of the data entered into any system component must be combined in Gate 124, then processed through Macrocell Scan Register (MSR) 126, and MSR 126 accepts only one piece of data at a time.
Once the programming operation is complete, in the usual case a verification operation is performed. Level Tester 106 performs the verification operation by performing a Margin High and a Margin Low test on signals from MSR 126. Margin High and Margin Low operations are stress tests designed to test a line or address at its upper and lower extremes. One skilled in the art would be familiar with suitable methods of level testing, including but not limited to using shift registers.
The problem with this prior art approach is that all programming operations must be executed in a serial fashion because the processing is executed through MSR 126. In addition to the increased time required by serial processing, this type of processing requires a relatively large number of test vectors. These factors can result in large memory load times when a device is being tested with automatic test equipment. The large number of test vectors is especially problematic in the case of in-system programming of embedded controllers. That is, to support in-system programming, a relatively large amount of memory is required to store the vectors associated with the verification process.
In view of the foregoing, it would be highly desirable to provide an improved verification scheme for macrocell based architectures in field programmable logic devices. Ideally, the scheme would reduce the number of required vectors and eliminate the need for an MSR. As a result, in-system programming via an embedded controller could be performed with reduced memory requirements. In addition, test time associated with automatic test equipment would be reduced.